How many registers does an x86-64 CPU have? (2020)
How many registers does an x86-64 CPU really have? This deep dive meticulously navigates the labyrinthine world of x86-64 architecture, laying out a rigorous methodology to count everything from general-purpose registers to obscure model-specific ones. It's a fascinating journey into the often-overlooked complexity that underpins modern computing, highlighting why such foundational knowledge is still relevant even in the age of new architectures like Apple Silicon.
The Lowdown
The article delves into the deceptively simple question of how many registers an x86-64 CPU possesses, quickly revealing the profound complexity behind the answer. Starting with clear ground rules for what to count (and what not to), the author meticulously categorizes and tallies various register types present in modern x86-64 processors, demonstrating that the number far exceeds common assumptions.
- Methodology & Ground Rules: The author establishes specific criteria, deciding to count sub-registers (like EAX for RAX) as distinct, include registers not usable in long mode, and exclude older or microarchitectural details. Model-specific registers (MSRs) are counted only if widely available and documented, with a detailed process for extracting counts from Intel's documentation.
- General-Purpose Registers (GPRs): These fundamental registers, along with their 8-, 16-, and 32-bit sub-registers, contribute significantly to the total, with 16 full-width GPRs fanning out to 52 sub-registers, totaling 68.
- Special and Segment Registers: Standard elements like RIP and RFLAGS (with its sub-registers EFLAGS/FLAGS) add 4, while the 6 segment registers (CS, SS, DS, ES, FS, GS) add another 6. Notably, FS and GS retain special functionality in long mode via MSRs.
- SIMD and FP Registers: A historical tour through x87, MMX, SSE, and AVX instruction sets. This section accounts for 8 x87 registers (plus 6 FPU control/status registers), 8 MMX registers (which overlap with x87), and a significant number of SSE/AVX registers (up to 33, including MXCSR and AVX-512 opmask registers, though AVX-512 was later partially excluded from the final count for broader compatibility reasons).
- Bounds, Debug, and Control Registers: Less frequently discussed but critical, these include 7 MPX bounds registers, 6 debug registers (DR0-DR3, DR6-DR7, noting the absence of DR4/DR5), and 6 core control registers (CR0-CR4, CR8) along with the extended XCR0.
- System Table Pointers: Registers like GDTR, LDTR, IDTR, and TR, which hold information for protected mode tables, add 4 entries.
- Model-Specific Registers (MSRs): The most numerous and complex category. After a rigorous filtering process involving PDF extraction and text analysis of Intel documentation, the author identifies approximately 400 architectural MSRs, far fewer than a naive count but still substantial.
The piece concludes that a typical x86-64 CPU core likely has roughly 557 registers, a number far greater than most developers might intuitively guess. The author acknowledges other potential registers, such as those related to APICs, Last Branch Records, or virtualization extensions, but defers their inclusion due to varying vendor implementations or memory-mapped nature.