RISC-V Is Sloooow
A Fedora developer's candid assessment highlights that current RISC-V hardware is 'sloooow' for package compilation, detailing significant build time discrepancies compared to other architectures. This blunt title sparked immediate debate on Hacker News, with many commenters emphasizing that the issue lies with early silicon implementations, not the RISC-V instruction set architecture itself. The discussion delves into the maturity curve of new ISAs and the ongoing quest for performant, rackable RISC-V server hardware.
The Lowdown
Marcin Juszkiewicz, a developer actively porting Fedora Linux to RISC-V, shares his experiences and frustrations regarding the performance of current RISC-V hardware. His work involves triaging issues, packaging, and building Fedora components, tasks that have brought the "slowness" of RISC-V to the forefront.
- Performance Bottleneck: RISC-V hardware currently available is significantly slower than other architectures for tasks like building packages. For instance, compiling 'binutils' takes 143 minutes on RISC-V compared to 29 minutes on x86_64, despite similar core counts.
- Hardware Limitations: Existing RISC-V builders typically feature low-end cores (comparable to Arm Cortex-A55) and limited RAM (8-32 GB), hindering build performance. To mitigate, Fedora's RISC-V port currently disables Link-Time Optimization (LTO).
- Emulation Advantage: The author notes that building large packages like 'llvm15' is significantly faster in QEMU (4 hours with 80 emulated cores) than on physical RISC-V hardware (10.5 hours on a Banana Pi BPI-F3).
- Future Hopes: While upcoming SoCs like UltraRISC UR-DP1000 and SpacemiT K3-based systems are expected to offer improvements, they are not seen as the "final solution." The author stresses the need for faster, rackable, and manageable server-grade hardware for RISC-V to become a primary architecture in Fedora Linux.
In conclusion, the article underscores the critical need for more powerful and server-ready RISC-V hardware to enable its viability as a primary architecture for robust Linux distributions like Fedora, despite promising progress on the software porting front.
The Gossip
Silicon Speed Sensations
Many commenters quickly pointed out that the article's title, "RISC-V Is Sloooow," is misleading. They argue that the slowness isn't inherent to the RISC-V ISA, but rather a characteristic of the *current implementations* and available silicon, which are often low-end or early-stage. The sentiment is that RISC-V, like ARM in its early days, will mature and eventually produce high-performance chips, distinguishing the architecture's potential from its present hardware reality.
Cross-Compilation Conundrums & Future Chips
A common suggestion to circumvent the slow native build times was cross-compilation. The discussion also touched upon the future landscape of high-performance RISC-V chips, with mentions of Tenstorrent's efforts and the likelihood of competitive RISC-V implementations emerging from China, potentially even adopting solutions like Loongson. There was also an inquiry about which specific RISC-V implementations are currently considered 'fast.'
s390x Speed Surprise
One commenter highlighted the surprisingly efficient performance of s390x (IBM Z Systems) in the provided build time comparison, noting its speed per core. This observation also came with a humorous remark about IBM's typical reticence in publicizing s390x performance benchmarks.