VHDL's Crown Jewel

This article praises VHDL's delta cycle algorithm as its key feature, enabling deterministic behavior in concurrent hardware description. It delves into how VHDL manages event ordering to prevent race conditions that are common in hardware simulation.

• VHDL's Delta Cycle: VHDL uses delta cycles to order events that occur in zero physical time. Signal value updates and process evaluations are handled in distinct phases within a delta cycle, ensuring determinism by processing all signal updates before subsequent process evaluations.
• Determinism Explained: The article illustrates how VHDL guarantees that processes always see the same signal values, regardless of internal execution order within update or evaluation sets, leading to predictable results.
• Verilog's Non-Determinism: In contrast, Verilog lacks a similar strict event ordering mechanism. Value updates and process evaluations can interleave, leading to non-deterministic outcomes depending on the simulator's execution order.
• Signals vs. Regs: VHDL's signals delay value updates to future delta cycles and are processed atomically, ensuring determinism. Verilog's regs (variables) are used for both internal computation and inter-process communication, leading to complexities.
• Nonblocking Assignments in Verilog: While Verilog's nonblocking assignments attempt to mitigate this by delaying updates, they are presented as a 'half-baked solution' as they only guarantee determinism for specific, synchronous design cases, not generally.
• Edge Cases: The author acknowledges VHDL has minor non-deterministic corners (shared variables, file I/O, asymmetric resolution functions) but notes they are rarely problematic in practice.

The author concludes that VHDL's delta cycle is a 'zero-cost solution for an important problem' that Verilog notably lacks, questioning the design choices of Verilog.