Aegis – open-source FPGA silicon
Aegis introduces a fully open-source FPGA, tackling the long-standing challenge of proprietary silicon in the field. This project provides an open fabric design, toolchain, and path to real silicon, offering a significant alternative to existing efforts. It appeals to Hacker News's enthusiasm for open-source hardware, democratizing complex technology, and challenging established industry norms.
The Lowdown
Aegis is an ambitious new project aiming to deliver a truly open-source Field-Programmable Gate Array (FPGA), breaking new ground in hardware design by making the silicon itself transparent and accessible. Unlike previous open-source FPGA endeavors that focused on reverse-engineering or tooling for proprietary hardware, Aegis starts from the ground up with an open fabric.
- The project's core innovation lies in its complete openness, encompassing the FPGA fabric design, the entire toolchain, and leveraging open-source Process Design Kits (PDKs) and shuttle services like wafer.space for fabrication.
- Aegis enables the generation of parameterized FPGA devices, featuring essential components such as LUT4s, Block RAMs (BRAM), Digital Signal Processors (DSPs), Serializers/Deserializers (SerDes), and sophisticated clock management tiles.
- The initial device, 'Aegis Terra 1,' is designed for the GF180MCU process and includes approximately 2880 LUT4s, 128 BRAM tiles, 64 DSP18 tiles, 224 I/O pads, 4 SerDes, and 2 clock tiles.
- A comprehensive open-source toolchain is provided for each device, covering synthesis (via Yosys), place and route (nextpnr-aegis), bitstream packing, and simulation.
- The project also outlines an ASIC tapeout pipeline, synthesizing the FPGA fabric itself into gate-level netlists and GDS2 files for foundry submission, supporting GF180MCU and Sky130 PDKs.
- The FPGA fabric's architecture, inspired by Xilinx-style conventions, is generated using ROHD (a Dart-based HDL framework) to produce synthesizable SystemVerilog, defining configurable logic blocks (CLB), tiles, and specialized blocks.
By offering a complete, transparent, and reproducible stack from design to fabrication, Aegis seeks to democratize FPGA development and foster innovation in open-source hardware, providing an exciting new pathway for designers and researchers.