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Floating Point Fun on Cortex-M Processors

This post dives deep into the arcane world of floating-point ABIs on ARM Cortex-M processors, clarifying the differences between 'soft', 'softfp', and 'hard' compilation options. It explains how these settings impact register usage, linker compatibility, and FPU hardware activation, using practical examples from the Zephyr RTOS. This level of low-level detail is catnip for embedded systems developers on HN.

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The Lowdown

The article 'Floating Point Fun on Cortex-M Processors' provides a highly technical breakdown of floating-point operations and Application Binary Interfaces (ABIs) within ARM Cortex-M microcontrollers. It illuminates how compiler flags dictate whether floating-point calculations leverage hardware FPU units or software emulation, and how arguments are passed to subroutines.

  • Floating Point ABIs: The author details three primary ARM floating-point ABIs: soft (software-emulated, integer register passing), softfp (hardware FPU, but soft-float calling conventions using integer registers), and hard (hardware FPU with FPU-specific calling conventions, utilizing FPU registers). This distinction is crucial for understanding linker errors.
  • Hardware and Registers: The post explains the role of ARM's C10 and C11 coprocessors and the dedicated floating-point register bank (s0-s31) for hard ABI. It clarifies that the term 'VFP' (Vector Floating Point) is still used for Cortex-M FPU despite 'FP' being more common.
  • Practical Examples: Using the nRF52840 and the Zephyr RTOS, the article demonstrates how to configure these ABIs (e.g., CONFIG_FPU, CONFIG_FP_SOFTABI) and inspect their effects through readelf output and assembly code disassembly for a simple addf function.
  • Dynamic FPU Control: A 'bonus round' explores how the FPU is initialized in Zephyr and, more importantly, how it can be dynamically enabled or disabled at runtime by directly manipulating System Control Space (SCS) registers like CPACR and FPCCR.
  • Fault Handling: It illustrates that attempting floating-point operations without an enabled FPU will trigger a 'NOCP (No Coprocessor) Usage Fault', and demonstrates how to enable the FPU 'just in time' to avoid such faults.

The article provides an essential guide for embedded developers navigating the complexities of floating-point support on Cortex-M, offering insights into compilation, runtime behavior, and low-level hardware control. It also teases future discussions on the trade-offs between hardware and software floating-point implementations.