I designed a nibble-oriented CPU in Verilog to build a scientific calculator
This project showcases an impressive, from-scratch implementation of a scientific calculator, designed entirely in hardware using a custom nibble-oriented CPU on an FPGA. It encompasses everything from Verilog and microcode to a full suite of simulation and synthesis tools. This deep dive into digital logic design and embedded systems resonates strongly with Hacker News's appreciation for fundamental engineering and practical, low-level builds.
The Lowdown
This ambitious project details the creation of a fully functional scientific calculator, built from the ground up on an FPGA. It features a custom-designed, nibble-oriented soft CPU, complete with its own microcode firmware, demonstrating a full-stack hardware and software co-design.
The project offers a comprehensive ecosystem, including:
- Custom CPU Design: A 'nibble-oriented CPU' implemented using Verilog, including the Arithmetic Logic Unit (ALU).
- Microcode Firmware: Firmware developed to control the custom CPU's operations.
- Development Toolchain: Verilog source files, Quartus project files for FPGA synthesis (specifically for Intel Cyclone II), and ModelSim for waveform simulation.
- Simulation & Debugging: A Qt-based simulator and debugger, along with a command-line test harness for hardware verification (both utilizing Verilator).
- Auxiliary Tools: Python scripts for microcode assembly and compilation.
- Accessible Demos: Web browser-based versions of the calculator, with and without a debugger, are available for immediate interaction.
- Research & Verification: A 'Pathfinding' section outlines independent projects for BCD arithmetic golden references, proofs of concept for complex operations, and input state machine simulations.
Ultimately, this project serves as a compelling example of fundamental digital design, taking a complex application like a scientific calculator and meticulously crafting its hardware and software layers from basic gates to a fully operational system.