z386: An Open-Source 80386 Built Around Original Microcode
An impressive project has resurrected the Intel 80386 CPU on an FPGA, named z386, by meticulously rebuilding its architecture around original Intel microcode. This deep technical dive allows old protected-mode DOS software and even Doom to run, showcasing a blend of digital archaeology and modern hardware implementation. It appeals to Hacker News's appreciation for complex reverse engineering, hardware design, and the nostalgic revival of foundational computing technology.
The Lowdown
z386 is an ambitious open-source project that recreates an Intel 80386-class CPU on an FPGA, driven by the original Intel microcode. Building on insights from a previous 8086 project (z8086), z386 has advanced to the point where it can successfully boot and run essential DOS environments like DOS 6/7, protected-mode applications like DOS/4GW, and classic games including Doom.
- Architectural Philosophy: Rather than emulation, z386 aims to reconstruct enough of the original 386 machine for the recovered microcode control ROM to drive it, maintaining structures like the 32-entry paging TLB and the Protection PLA.
- Performance Metrics: The current z386 build performs comparably to a fast 70MHz cached 386 or a low-end 486, with detailed comparisons provided against the existing ao486 FPGA core in terms of resource usage and gaming FPS.
- Key Architectural Units: The article meticulously breaks down how z386 implements the 386's eight major units: Prefetch, Decoder, Microcode Sequencer, ALU/Shifter, Segmentation, Protection, Paging, and the Bus Interface Unit (BIU) with cache and memory path.
- Instruction Handling: It delves into the complexities of x86 instruction prefetch and decode, explaining how the decoder, supported by PLA-style tables, translates variable-length instructions into a 111-bit decoded word for the execution unit.
- Microcode in Action: The core of the project, the 37-bit wide 80386 microcode, is detailed, illustrating how it dictates internal operations, ALU functions, memory cycles, and control flow. The article explains crucial concepts like two-cycle minimum instructions, delay slots, and conditional instruction termination (
RNIvariants). - Cache Implementation: To enhance performance and mitigate SDRAM latency, z386 incorporates a 16KB, 4-way set-associative, unified L1 cache. It utilizes a VIPT-style lookup to enable parallel address translation and cache access, prioritizing a high core clock over maximum capacity.
- Rigorous Testing: The project employs a multi-layered testing strategy, starting with real-mode and protected-mode single-step fuzz tests against a reference (86Box), progressing to hand-written programs for complex scenarios, and finally validating against full-system integration with real software like SeaBIOS, DOS extenders, and games.
- Project Evolution: A timeline outlines the rapid development, from parsing the control ROM and establishing real-mode instruction coverage in January to running Doom and optimizing for various FPGA families by April.
In essence, z386 is lauded as both an educational reconstruction and a usable FPGA CPU. The author reflects on the 80386's historical significance as Intel's foundational 32-bit x86 processor and emphasizes how reverse-engineered microcode provides unparalleled insight into the original design's intricate details and implicit hardware contracts.