Samsung Demonstrates 3D Stacked FETs with Triple Nanosheet Channels at 42nm
Samsung has unveiled a groundbreaking 3D Stacked FET architecture, featuring triple nanosheet channels at a 42nm gate pitch, which builds upon the Gate-All-Around (GAA) design. This innovation signals a critical shift in semiconductor manufacturing, moving transistor integration from a two-dimensional plane to a vertical stacking approach. The development promises higher transistor density and improved performance, addressing the physical scaling limits faced by conventional chip designs and pushing the boundaries of future logic devices.
The Lowdown
Samsung's Semiconductor Research Center recently presented a highly-acclaimed paper at the 2026 VLSI Symposium, detailing their pioneering work on 3D Stacked FETs. This research introduces a new paradigm for transistor architecture, moving beyond traditional planar layouts to vertically stack transistors, thereby enabling greater density and continued scaling for advanced logic applications.
- Evolution of Transistors: The industry has seen an evolution from planar transistors to FinFETs, and then to Gate-All-Around (GAA) structures. The 3D Stacked FET is presented as the next logical step, extending GAA into the vertical dimension.
- Why Vertical Stacking?: Analogous to urban development building skyscrapers when land is scarce, vertical stacking allows for more transistors within the same chip area, overcoming the density limitations of side-by-side arrangements.
- Key Challenges & Solutions: The research addressed three primary hurdles for 3D Stacked FETs:
- Current Conduction Paths: Solved by implementing triple-stacked nanosheet channels, ensuring sufficient current drive despite a compact footprint.
- High-Quality Current Paths: Achieved through advanced epitaxial growth techniques, creating uniform, defect-free silicon crystal layers across multiple stacked channels.
- Electrical Isolation: Managed using Middle Dielectric Isolation (MDI), a crucial layer that precisely separates and prevents interference between the vertically stacked n-type and p-type transistors.
- Scaling Achievement: The demonstration of a 3D Stacked FET with a gate pitch of just 42 nm signifies a major step towards practical implementation, proving that the technology can achieve the precision required for next-generation devices.
- Validated Performance: The team successfully demonstrated effective current control and high device uniformity across both n-type and p-type transistors within the 42 nm gate-pitch 3D Stacked FETs.
This work underscores that the future of logic semiconductors is expanding into the third dimension. By addressing complex fabrication challenges, Samsung's 3D Stacked FETs represent a vital pathway for continuing Moore's Law and enhancing the capabilities of future computing technologies.