RISC-V: They Should Have Known Better

Dmitry.GR presents a comprehensive and highly critical analysis of the RISC-V instruction set architecture, aiming to debunk common misconceptions and highlight what he perceives as fundamental design flaws. He contends that RISC-V's aspiration to dominate all computing segments, from tiny microcontrollers to supercomputers, is unrealistic due to inherent architectural compromises. The author argues that RISC-V proponents, particularly from academic backgrounds, have ignored decades of ISA design lessons, leading to a specification rife with practical problems.

• "Everything for Everyone" Fallacy: RISC-V attempts to be optimal for all use cases, which is inherently impossible due to conflicting design requirements for high-end CPUs (focused on throughput) and microcontrollers (focused on interrupt latency and code density). The author predicts RISC-V will only dominate the "cheap-as-dirt single-use microcontroller" space, and even there, it's despite its ISA design. The bar is so low, it's an improvement over 8051. The article highlights that RISC-V is notably worse than Cortex-M0 for interrupt handling in microcontrollers, requiring significantly more cycles.
• Inefficient Encoding and Missing Features: The article heavily criticizes RISC-V's instruction encoding, particularly for compressed instructions and immediates, calling it "ridiculous" and a "jigsaw puzzle." It points out poor design choices like limited offset ranges for memory operations in compressed instructions and the absence of obvious, useful instructions like "test bit and branch" or comprehensive bitfield operations, which are common and trivial to implement in hardware in other architectures. The late addition of extensions like Zba (for array addressing) is also seen as a sign of initial oversight.
• Excessive Optionality and Fragmentation: A central criticism is the extreme optionality of core features (multiplication, division, user/supervisor modes, CSRs). This leads to severe fragmentation, making it nearly impossible to write portable software or guarantee feature availability. The misa register, intended for feature detection, is itself optional and unreliable, and the architecture struggles with basic tasks like detecting the current CPU mode. The introduction of "profiles" like RVA23 to standardize optional extensions is deemed a belated, committee-driven fix that further fragments the ecosystem, as much existing "RISC-V" hardware is not RVA23 compliant.
• Academic Roots and Future Outlook: The author attributes these design choices to a "not invented here" syndrome prevalent in academia, where real-world practicality was overlooked in favor of a clean-slate approach. Despite these flaws, the author acknowledges RISC-V's inevitable success in cost-sensitive markets (cheap microcontrollers, ML accelerators) due to its royalty-free nature. However, he maintains it is ill-suited for high-performance desktop or server markets, where better-designed, albeit proprietary, architectures like Aarch64 will continue to dominate. He argues RISC-V's market gains will be due to being "cheap," not "good."

In conclusion, Dmitry.GR paints a picture of RISC-V as an academically interesting but fundamentally flawed ISA, whose open nature may secure it niches in the market but whose design decisions prevent it from becoming a top-tier general-purpose computing platform. The article's detailed technical breakdowns serve as a cautionary tale against design-by-committee and the neglect of practical engineering wisdom.